The present invention relates to a high integrated semiconductor memory device using a low level of power supply voltage, and more particularly to a boosting voltage circuit which is capable of detecting the boosting voltage level in such a device.
Recently, as dynamic random access memory (dynamic RAM) design tends toward higher density and lower power consumption, a boosting voltage Vpp generator is often employed in a chip so as to prevent the deterioration of, for example, word line driving capability. This boosting voltage Vpp has a higher voltage level than an internally used power supply voltage Vcc and serves to raise a word line driving voltage attenuated because of the high density of the device. To read data "1" stored in memory cells, a sufficient voltage difference should be formed in distributing a charge between the memory cells and bit lines. To this end, a sufficient level of voltage has to be supplied to the word line so that cell transistors can be fully turned on. However, since this effect cannot be obtained with a lowered power supply voltage Vcc, such a boosting voltage Vpp having more than a potential of Vcc+Vth (where Vth is a threshold voltage of the cell transistor) becomes necessary.
As well known in the related art, methods of maintaining the potential of the boosting voltage Vpp are as follows. In a stand-by state, the Vpp level is detected through a level detector for stand-by. Whenever the detected level is lower than a predetermined reference level, a boosting voltage generator for stand-by is driven to raise the detected level to the reference level. Whenever the detected level is higher than or equal to the reference level, an operation of the boosting voltage generator for stand-by is stopped. However, since a typical boosting voltage generator for stand-by has a small capacity, another boosting voltage generator for active cycle having a great large capacity is further needed so as to supplement a charge amount of the boosting voltage consumed during the active cycle.
FIG. 1 shows a conventional voltage boosting circuit configuration. A chip master clock generator 1 chip generates a master clock .phi.R in response to a row address strobe signal RASB. A boosting voltage generator control circuit 2 generates a boosting voltage generator control signal .phi.PC every active cycle in response to the chip master clock .phi.R. First and second boosting voltage generators 3 and 4, which are respectively used for stand-by cycle and active cycle, are selectively operated under control of the signal .phi.PC. As shown in FIGS. 2 to 5, the first and second boosting voltage generators 3 and 4 are operated in a complementary relation in accordance with the signal .phi.PC. In the active cycle where the signal RASB is in a logic "low" level, the first boosting voltage generator 3 generates the boosting voltage Vpp, and in the stand-by cycle where the signal RASB is in a logic "high" level, the second boosting voltage generator 4 generates the boosting voltage Vpp. Referring to FIG. 4, during the stand-by cycle where the signal .phi.PC is in the logic "low" level, a potential on a node 5 is raised by a MOS capacitor 7, and the raised potential is transmitted through a diode-connected NMOS transistor 10 for transmission to a node 6. When the signal .phi.PC is changed from the logic "low" level to the logic "high" level (the signal RASB falls to the logic "low" level and the active cycle is started), the potential on the node 6 is again boosted by a MOS capacitor 12 and generated as the boosting voltage Vpp through a diode-connected NMOS transistor 11.
Here, by accurately detecting the charge amount of the Vpp consumed every active cycle, the capacity of the boosting voltage generator for the active cycle should be set to supply the detected charge amount of the Vpp. However, in the configuration of FIG. 1, there are problems in that the charge consumption amount of the Vpp is not accurately consistent with the capacity of the boosting voltage generator, and in the case where the capacity of the boosting voltage generator is larger than the charge consumption amount of the Vpp, the reliability of chip is deteriorated due to extended current consumption and high electric field.